Physical Design Engineer

AMD · Bangalore

Source and collection record

Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 88012

Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.

How sourcing and classification work · Report a discrepancy

Your application evidence checklist

Mark the statements you can support after reading the employer source. This checklist stays on this page; it does not score your eligibility or submit an application.

Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

0 of 3 checks marked. Keep unresolved requirements as questions for the employer.

Collected role description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. <span style="margin: 0px; padding: 0px;" data-ccp-charstyle="normaltextrun" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|105","ClassId":1073872969,"Properties":[469775450,"normaltextrun",201340122,"1",134233614,"true",469778129,"normaltextrun",335572020,"1",469778324,"Default Paragraph Font"]}">MTS SILICON DESIGN ENGINEER<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="eop" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|106","ClassId":1073872969,"Properties":[469775450,"eop",201340122,"1",134233614,"true",469778129,"eop",335572020,"1",469778324,"Default Paragraph Font"]}"> <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335551550":2,"335551620":2,"335559738":0,"335559739":0,"335559740":240}"> <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> THE ROLE: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON:AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBLITIES: <ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Implementing RTL to GDS2 flow</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Deft at Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Tasks to include Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Identify complex technical problems, break them down, summarize multiple possible solutions,</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Drive and hands-on flow development and scripting</li></ul> PREFERRED EXPERIENCE: <ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">8+years of professional experience in physical design, preferably with high performance designs.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Versatility with scripts to automate design flow.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Excellent physical design and timing background.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Good understanding of computer organization/architecture is preferred.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong analytical/problem solving skills and pronounced attention to details</li></ul>ACADEMIC CREDENTIALS: <ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="11" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="3" data-aria-level="1"><span style="margin: 0px; padding: 0px;" data-ccp-parastyle="paragraph" data-ccp-parastyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|104","ClassId":1073872969,"Properties":[469775450,"paragraph",201340122,"2",134233614,"true",469778129,"paragraph",335572020,"1",469777841,"Times New Roman",469777842,"Times New Roman",469777843,"Times New Roman",469777844,"Times New Roman",469769226,"Times New Roman",268442635,"24",335559740,"240",201341983,"0",134233118,"true",134233117,"true",469778324,"Normal"]}">Bachelors or Masters degree in computer engineering/Electrical Engineering</li></ul> #LI-AB1 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="normaltextrun" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|105","ClassId":1073872969,"Properties":[469775450,"normaltextrun",201340122,"1",134233614,"true",469778129,"normaltextrun",335572020,"1",469778324,"Default Paragraph Font"]}">MTS SILICON DESIGN ENGINEER<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="eop" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|106","ClassId":1073872969,"Properties":[469775450,"eop",201340122,"1",134233614,"true",469778129,"eop",335572020,"1",469778324,"Default Paragraph Font"]}"> <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335551550":2,"335551620":2,"335559738":0,"335559739":0,"335559740":240}">  <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> THE ROLE: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON:AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBLITIES: <ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Implementing RTL to GDS2 flow</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Deft at Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Tasks to include Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Identify complex technical problems, break them down, summarize multiple possible solutions,</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Drive and hands-on flow development and scripting</li></ul> PREFERRED EXPERIENCE: <ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">8+years of professional experience in physical design, preferably with high performance designs.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Versatility with scripts to automate design flow.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Excellent physical design and timing background.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Good understanding of computer organization/architecture is preferred.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong analytical/problem solving skills and pronounced attention to details</li></ul>ACADEMIC CREDENTIALS:  <ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="11" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="3" data-aria-level="1"><span style="margin: 0px; padding: 0px;" data-ccp-parastyle="paragraph" data-ccp-parastyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|104","ClassId":1073872969,"Properties":[469775450,"paragraph",201340122,"2",134233614,"true",469778129,"paragraph",335572020,"1",469777841,"Times New Roman",469777842,"Times New Roman",469777843,"Times New Roman",469777844,"Times New Roman",469769226,"Times New Roman",268442635,"24",335559740,"240",201341983,"0",134233118,"true",134233117,"true",469778324,"Normal"]}">Bachelors or Masters degree in computer engineering/Electrical Engineering</li></ul> #LI-AB1

Collected experience requirement

8+ years