Lead RTL design Engineer

AMD · Bangalore

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Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 88802

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Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

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Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. Lead RTL Design Engineer<div><h3>Role</h3>As part of the SoC Design team, the engineer has technical responsibility for SoC design and integration efforts involving both AMD and third-party IPs. The role works closely with IP development, verification, front-end integration, and physical design teams throughout the SoC development cycle.<h3>Key Responsibilities</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">SoC-level design and integration.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Integration of IPs, SoC fabric, voltage crossings, clock crossings, resets, fuses, and I/O.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">RTL design and coding for SoC logic and features.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">SoC power design and power implementation activities. </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Static verification including:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">RTL Lint</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">CDC (Clock Domain Crossing)</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">RDC (Reset Domain Crossing)</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Power checks</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Connectivity checks </li></ul></li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Debugging simulation and integration issues spanning multiple IPs in collaboration with verification teams.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Supporting top-level synthesis and collaborating with physical design teams for full-chip implementation. Leading one of the design domains (integration, power, CDC/RDC, connectivity, etc.). <a href="https://amdcloud-my.sharepoint.com/personal/sanshind_amd_com/_layouts/15/Doc.aspx?sourcedoc=%7BAF2D4D71-30F9-4FF7-8043-D78E9402E4D2%7D&file=JD%20S3%20MTS%20SOC%20Design.docx&action=default&mobileredirect=true&DefaultItemOpen=1">]</a></li></ul><h3>Required Skills</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Verilog RTL development in CPU, SoC, or ASIC environments. </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong understanding of:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">SoC integration</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">SoC architecture</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">System interconnect protocols such as AXI and PCIe </li></ul></li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">UPF and low-power methodologies</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Static timing analysis (STA)</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Physical design interaction and implementation requirements </li></ul></li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Familiarity with scripting languages such as Tcl, Perl, Ruby, or Shell. </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge of formal verification techniques and tools.</li></ul><h3>Personal Attributes</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Self-driven and able to work independently. </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong written and verbal communication skills. </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong problem-solving capability. </li></ul><h3>Experience & Education</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">8+ years of SoC Design and Verilog RTL development experience. </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">BE/B.Tech/ME/M.Tech (ECE/EEE or equivalent). </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">. </li></ul><ul><li>#LI-SR5</li></ul></div> Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

Lead RTL Design Engineer<div><h3>Role</h3>As part of the SoC Design team, the engineer has technical responsibility for SoC design and integration efforts involving both AMD and third-party IPs. The role works closely with IP development, verification, front-end integration, and physical design teams throughout the SoC development cycle.<h3>Key Responsibilities</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">SoC-level design and integration.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Integration of IPs, SoC fabric, voltage crossings, clock crossings, resets, fuses, and I/O.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">RTL design and coding for SoC logic and features.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">SoC power design and power implementation activities. </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Static verification including:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">RTL Lint</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">CDC (Clock Domain Crossing)</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">RDC (Reset Domain Crossing)</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Power checks</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Connectivity checks </li></ul></li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Debugging simulation and integration issues spanning multiple IPs in collaboration with verification teams.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Supporting top-level synthesis and collaborating with physical design teams for full-chip implementation. Leading one of the design domains (integration, power, CDC/RDC, connectivity, etc.). <a href="https://amdcloud-my.sharepoint.com/personal/sanshind_amd_com/_layouts/15/Doc.aspx?sourcedoc=%7BAF2D4D71-30F9-4FF7-8043-D78E9402E4D2%7D&file=JD%20S3%20MTS%20SOC%20Design.docx&action=default&mobileredirect=true&DefaultItemOpen=1">]</a></li></ul><h3>Required Skills</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Verilog RTL development in CPU, SoC, or ASIC environments. </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong understanding of:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">SoC integration</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">SoC architecture</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">System interconnect protocols such as AXI and PCIe </li></ul></li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">UPF and low-power methodologies</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Static timing analysis (STA)</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Physical design interaction and implementation requirements </li></ul></li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Familiarity with scripting languages such as Tcl, Perl, Ruby, or Shell. </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge of formal verification techniques and tools.</li></ul><h3>Personal Attributes</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Self-driven and able to work independently. </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong written and verbal communication skills. </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong problem-solving capability. </li></ul><h3>Experience & Education</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">8+ years of SoC Design and Verilog RTL development experience. </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">BE/B.Tech/ME/M.Tech (ECE/EEE or equivalent). </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">. </li></ul><ul><li>#LI-SR5</li></ul></div>

Collected experience requirement

8+ years