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Senior DFT Design Engineer (ATPG/Scan stitching)

AMD · Hyderabad

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Collected role description

<strong class="jdheading"></strong><br><br><p style="margin: 0px; padding: 0px; color: windowtext;"><strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">WHAT YOU DO AT AMD CHANGES EVERYTHING</span></span></strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-ccp-props="{}"> </span></p><p style="margin: 0px; padding: 0px; color: windowtext;"><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, </span><span style="margin: 0px; padding: 0px;">gaming</span><span style="margin: 0px; padding: 0px;"> and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human </span><span style="margin: 0px; padding: 0px; border-bottom: 1px solid transparent;">ingenuity</span><span style="margin: 0px; padding: 0px;"> and a shared passion to create something extraordinary. When you join AMD, </span><span style="margin: 0px; padding: 0px;">you’ll</span><span style="margin: 0px; padding: 0px;"> discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.</span><span style="margin: 0px; padding: 0px;"> </span></span><strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">Together, we advance your career. </span></span></strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-ccp-props="{}"> </span></p> <br><strong class="jdheading"></strong><br><br><p style="margin: 0px; padding: 0px; color: windowtext;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="margin: 0px; padding: 0px;" data-contrast="auto"><span style="margin: 0px; padding: 0px;" data-ccp-charstyle="eop"> </span></span><span style="font-weight: bold;">THE ROLE:</span> </span></p><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">We are looking for an adaptive, self-motivative DFT engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The DFT team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. </span></p><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;"> </p><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-weight: bold;">THE PERSON:</span> </span></p><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">You have a passion for modern, digital design, and DFT in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. </span></p><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;"> </p><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-weight: bold;">KEY RESPONSIBILITIES:</span> </span></p><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="color: #32363a;">Implementation and verification of DFT features like </span>SCAN, MBIST, LBIST and JTAG</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="color: #32363a;">Support </span>Spyglass-DFTDRC debug and coverage correlation</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #32363a;">Scan insertion and ATPG pattern generation </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #32363a;">ATPG patterns verification with gate-level simulation </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #32363a;">Test coverage and test cost reduction analysis </span></li></ul><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: #32363a; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Post silicon support to ensure successful bring up and enhance yield learning</span></li></ul><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;"> </p><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-weight: bold;">PREFERRED EXPERIENCE:</span> </span></p><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience in scan-stitching; and has good knowledge of scan-stitching related concepts</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Exposure to MBIST/BISR implementation and with the Tessent flow of mbist-insertion</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Excellent hands-on ATPG; and is well conversed with the files required to run ATPG</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge/experience with Tessent ATPG (mentor) is a plus</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge on Spyglass-DFT</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Excellent hands-on debug skills and scripting skills are critical</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge on automation scripts like TCL/AWK/SED is a plus</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Understands the basics of JTAG</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with post-silicon bring up is a plus</span></li></ul><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;"> </p><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-weight: bold;">ACADEMIC CREDENTIALS:</span> </span></p><p style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Bachelors degree w/7+ years or Masters degree w/5+ years in Electronics engineering/Electrical Engineering</span></p><p style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"> </p><p style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif;"> </p><p style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">#LI-SS1</span></p> <br><strong class="jdheading"></strong><br><br><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">Benefits offered are described: </span></em><span style="font-family: 'Arial',sans-serif; color: black;"><a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>.</span></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.</span></em></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a></span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;"> </span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">This posting is for an existing vacancy.</span></em></span></p>

Collected minimum qualification

<p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">Benefits offered are described:&nbsp; </span></em><span style="font-family: 'Arial',sans-serif; color: black;"><a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>.</span></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;">&nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.&nbsp;&nbsp; We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</span></em></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;">&nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.&nbsp; AMD&rsquo;s &ldquo;Responsible AI Policy&rdquo; is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a></span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">&nbsp;</span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">This posting is for an existing vacancy.</span></em></span></p>

Collected preferred qualification

<p style="margin: 0px; padding: 0px; color: windowtext;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="margin: 0px; padding: 0px;" data-contrast="auto"><span style="margin: 0px; padding: 0px;" data-ccp-charstyle="eop"> </span></span><span style="font-weight: bold;">THE ROLE:</span>&nbsp;</span></p><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">We are looking for an adaptive, self-motivative DFT engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The DFT&nbsp;team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.&nbsp;</span></p><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;">&nbsp;</p><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-weight: bold;">THE PERSON:</span>&nbsp;</span></p><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">You have a passion for modern, digital design, and DFT in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.&nbsp;</span></p><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;">&nbsp;</p><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-weight: bold;">KEY RESPONSIBILITIES:</span>&nbsp;</span></p><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="color: #32363a;">Implementation and verification of DFT features like </span>SCAN, MBIST, LBIST and JTAG</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="color: #32363a;">Support </span>Spyglass-DFTDRC debug and coverage correlation</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #32363a;">Scan insertion and ATPG pattern generation&nbsp;</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #32363a;">ATPG patterns verification with gate-level simulation&nbsp;</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #32363a;">Test coverage and test cost reduction analysis&nbsp;</span></li></ul><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: #32363a; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Post silicon support to ensure successful bring up and enhance yield learning</span></li></ul><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;">&nbsp;</p><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-weight: bold;">PREFERRED EXPERIENCE:</span>&nbsp;</span></p><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience in scan-stitching; and has good knowledge of scan-stitching related concepts</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Exposure to MBIST/BISR implementation and with the Tessent flow of mbist-insertion</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Excellent hands-on ATPG; and is well conversed with the files required to run ATPG</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge/experience with Tessent ATPG (mentor) is a plus</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge on Spyglass-DFT</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Excellent hands-on debug skills and scripting skills are critical</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge on automation scripts like TCL/AWK/SED is a plus</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Understands the basics of JTAG</span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with post-silicon bring up is a plus</span></li></ul><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;">&nbsp;</p><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-weight: bold;">ACADEMIC CREDENTIALS:</span>&nbsp;</span></p><p style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Bachelors degree w/7+ years or Masters degree w/5+ years in Electronics engineering/Electrical Engineering</span></p><p style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">&nbsp;</p><p style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif;">&nbsp;</p><p style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">#LI-SS1</span></p>

Collected experience requirement

7+ years