Debug Lead Engineer

<strong class="jdheading"></strong><br><br><p style="margin: 0px; padding: 0px; color: windowtext;"><strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">WHAT YOU DO AT AMD CHANGES EVERYTHING</span></span></strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-ccp-props="{}"> </span></p><p style="margin: 0px; padding: 0px; color: windowtext;"><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, </span><span style="margin: 0px; padding: 0px;">gaming</span><span style="margin: 0px; padding: 0px;"> and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human </span><span style="margin: 0px; padding: 0px; border-bottom: 1px solid transparent;">ingenuity</span><span style="margin: 0px; padding: 0px;"> and a shared passion to create something extraordinary. When you join AMD, </span><span style="margin: 0px; padding: 0px;">you’ll</span><span style="margin: 0px; padding: 0px;"> discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.</span><span style="margin: 0px; padding: 0px;"> </span></span><strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">Together, we advance your career. </span></span></strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-ccp-props="{}"> </span></p> <br><strong class="jdheading"></strong><br><br><p style="margin: 0in; font-family: Arial; font-size: 11pt; color: black;"><span style="font-weight: bold;">Debug Lead Engineer</span></p><p style="margin: 0in; font-family: Arial; font-size: 11pt; color: black;"> </p><p style="margin: 0in; font-family: Arial; font-size: 11pt; color: black;"><span style="font-weight: bold;">Roles & Responsibilities for Lead System Engineer: </span> </p><ol style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in; font-family: Arial; font-size: 11pt; font-weight: normal; font-style: normal;" type="1"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;" value="1"><span style="font-family: Arial; font-size: 11pt; font-weight: normal; font-style: normal;">Assume technical responsibility from Pre-silicon to Post-silicon environment for Feature enablement and SoC-System level flow for use cases. </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Pre-Silicon: New SOC features enablement, implementation and coverage plan in Emulation </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Pre-silicon: Review all Silicon bugs that deferred out SOC Tape out and ensure it does not impact the system level features / use cases. </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Post Silicon: Lead the Bring-up planning in collaboration with Silicon teams, Platform, Firmware / BIOS, Post Si Validation team so we have the fastest and functional bring-up as soon as silicon arrives in the lab. </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Post Silicon: Partner with SOC NPI PM and be the technical lead to support & debug SOC related challenges from Tape out all the way to SOC IP milestone. </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Post Silicon: Lead cross-functional critical silicon issue debug, uplevel and communicate the updates into core teams and Management program reviews. </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Post Silicon: Provide inputs to Silicon Validation teams on coverage for New SOC features, enablement, implementation, IPs, and functional coverage at the system level. </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Exhibit strong technical leadership on X86 architecture and associated feature implementation </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Exhibit great technical depth in the post silicon enablement and validation of both HW and FW aspects to take the right technical decisions for the team </span></li></ol><p style="margin: 0in; font-family: Calibri; font-size: 11pt;"> </p><p style="margin: 0in; font-family: Arial; font-size: 11pt; color: black;"><span style="font-weight: bold;">Individual requirements:</span> </p><ol style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in; font-family: Arial; font-size: 12pt; font-weight: normal; font-style: normal;" type="1"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;" value="1"><span style="font-family: Arial; font-size: 12pt; font-weight: normal; font-style: normal;">Highly skilled engineering professional with over 15 years of experience.</span></li></ol><ol style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in; font-family: Arial; font-size: 11pt; font-weight: normal; font-style: normal;" type="1"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;" value="2"><span style="font-family: Arial; font-size: 11pt; font-weight: normal; font-style: normal;">Solid experience in both Pre and Post Silicon enablement and validation with strong BIOS/FW/SW intercepting knowledge. </span></li></ol><ol style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in; font-family: Arial; font-size: 11pt; font-weight: normal; font-style: normal;" type="1"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;" value="2"><span style="font-family: Arial; font-size: 11pt; font-weight: normal; font-style: normal;">Solid Experience and Knowledge in the HW and FW aspects of X86 design </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Solid experience in connecting the bigger picture across different related domains between Hardware/Firmware and Software and com </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Adept in calling out risks while anticipating issues and coming up with appropriate mitigation plans </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Experienced in working with the Enablement Manager and Leads, Program Managers, Product Managers, BIOS/FW Managers and other cross functional stakeholders and create a robust alignment setup while running execution. </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Preferred experience working with cross-functional teams like DV/Silicon Designers/Pre-silicon/Platform/BIOS/FW/ SW. </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Experience in High Speed I/Os like PCIe (preferably Gen4 and above), Memory (DDR4/DDR5.LPDDR4/LPDDR5), USB4.0/3.2/3.1, USB PD, USB Type C, Display interfaces and Ethernet and high-speed interconnects. </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Experience in Power Management </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Hands-on high speed and board measurement techniques in using high end equipment like Oscilloscopes, Logic Analyzers, Debugger tools, Raspberry PI, Network analyzers, etc. </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Preferred experience with scripting using TCL, Python </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Excellent communication, collaboration, articulation, upleveling to senior management and team playing skills. </span></li></ol><p style="margin: 0in; font-family: Calibri; font-size: 11pt;"> </p><p style="margin: 0in; font-family: Arial; font-size: 11pt; color: black;"><span style="font-weight: bold;">Key responsibilities:</span> </p><ol style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in; font-family: Arial; font-size: 11pt; font-weight: normal; font-style: normal;" type="1"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;" value="1"><span style="font-family: Arial; font-size: 11pt; font-weight: normal; font-style: normal;">Synergize with the Pre-silicon and DV teams and other stakeholders for proper interception of milestones and risk callouts. </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Actively participate in discussions with cross-functional teams in defining and refining test plans and guiding the team for the right path. </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Be on top of all issues pertinent to Debug & Triage of any functional issues across the entire validation cycle </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Drive meetings for issue closures and actively track schedules and milestone quality metrics </span></li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"><span style="font-family: Arial; font-size: 11pt;">Ensure the Best-in-class Documentation and collateral delivery from the team. </span></li></ol><p style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: black;"> </p><p>#L1-RG2</p> <br><strong class="jdheading"></strong><br><br><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">Benefits offered are described: </span></em><span style="font-family: 'Arial',sans-serif; color: black;"><a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>.</span></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.</span></em></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a></span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;"> </span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">This posting is for an existing vacancy.</span></em></span></p>