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RTL Design Engineer

AMD · Hyderabad

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Collected role description

<strong class="jdheading"></strong><br><br><p style="margin: 0px; padding: 0px; color: windowtext;"><strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">WHAT YOU DO AT AMD CHANGES EVERYTHING</span></span></strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-ccp-props="{}"> </span></p><p style="margin: 0px; padding: 0px; color: windowtext;"><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, </span><span style="margin: 0px; padding: 0px;">gaming</span><span style="margin: 0px; padding: 0px;"> and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human </span><span style="margin: 0px; padding: 0px; border-bottom: 1px solid transparent;">ingenuity</span><span style="margin: 0px; padding: 0px;"> and a shared passion to create something extraordinary. When you join AMD, </span><span style="margin: 0px; padding: 0px;">you’ll</span><span style="margin: 0px; padding: 0px;"> discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.</span><span style="margin: 0px; padding: 0px;"> </span></span><strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">Together, we advance your career. </span></span></strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-ccp-props="{}"> </span></p> <br><strong class="jdheading"></strong><br><br><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">ASIC RTL DESIGN ENGINEER</span></strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> </span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> </span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">THE ROLE:</span></strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> </span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">This exciting position in AMD's Silicon IP solutions & SOC group will provide the individual with an opportunity to demonstrate strong technical leadership across the design hierarchy from architecture to Productization. Join us in providing innovative IP solutions as we embark on our journey into the cutting edge programmable logic based silicon designs by delivering the complex IP Solutions for multiple market segments</span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> </span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">As an MTS you will work as part of a team responsible for all phases of product development including product definition and delivery. Member Technical Staff is expected to participate in and lead many aspects of a technical project including: thorough understanding of IP Architectural definition, u-Architecture development for individual IPs or IP subsystems, leading cross-functional IP teams from front-end development through Productization & ASICization.</span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> </span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">This position requires an individual to be creative, team-oriented, technology savvy, able to lead large cross-functional teams, comfortable and willing to provide regular updates to management chain during the project execution </span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> </span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">THE PERSON:</span></strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> </span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">You have a passion for modern, complex hardware and IP architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. </span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> </span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">KEY RESPONSIBILITIES:</span></strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> </span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> </span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">A major part of your responsibility will be to participate in and take a lead technical role in most of the phases of the product development cycle from new product exploration, architecture through implementation, prototyping, validation and support including: </span></p><ul style="margin-top: 0in;"><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Define u-architecture from the architecture definition</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Evaluating and executing design and development plans for IPs </span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">RTL design, IP Integration & documentation </span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Participating in and acting as a senior technical reviewer for various u-architecture and implementation reviews within the development organization</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Working with stakeholders to develop comprehensive testing plans including Compliance and Interop testing</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Critically Review and provide feedback on the Design Implementations and Verification plans</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Acting as technical mentor to junior engineers</span></li></ul><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> </span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">PREFERRED EXPERIENCE:</span></strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> </span></p><ul style="margin-top: 0in;"><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">A minimum of 8 years of experience is required. </span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Proven experience in Silicon IP development process, methodologies, Design for Test methodologies</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Experience with Verilog RTL design, VCS simulation tool, Perl/Shell scripting</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Proven experience in contributing to complex silicon tapeouts</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Detailed understanding and proven track record of developing any of the leading edge PCIe, Full featured DMAs, NVMe based Storage IP, networking IP solutions such as Ethernet, TCP/IP, RDMA IPs.</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Strong oral and written communication skills are essential</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">The ideal candidate will be a proactive contributor to the RTL design methodologies </span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Ability to work on complex issues where analysis situations or data requires an in-depth evaluation of variable factors.</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">To be successful, this individual must demonstrate favorable results through leadership and influencing multiple individuals and groups. </span></li></ul><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> </span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">ACADEMIC CREDENTIALS:</span></strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> </span></p><ul style="margin-top: 0in;"><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">A Bachelor of Science Degree in Electrical Engineering or Computer Science, a master’s degree or equivalent experience is required.</span></li></ul><p><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="line-height: 107%;">#LI-PP2</span></span></span></p> <br><strong class="jdheading"></strong><br><br><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">Benefits offered are described: </span></em><span style="font-family: 'Arial',sans-serif; color: black;"><a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>.</span></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.</span></em></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a></span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;"> </span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">This posting is for an existing vacancy.</span></em></span></p>

Collected minimum qualification

<p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">Benefits offered are described:&nbsp; </span></em><span style="font-family: 'Arial',sans-serif; color: black;"><a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>.</span></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;">&nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.&nbsp;&nbsp; We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</span></em></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;">&nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.&nbsp; AMD&rsquo;s &ldquo;Responsible AI Policy&rdquo; is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a></span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">&nbsp;</span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">This posting is for an existing vacancy.</span></em></span></p>

Collected preferred qualification

<p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">ASIC RTL DESIGN ENGINEER</span></strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> &nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> &nbsp;</span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">THE ROLE:</span></strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">&nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">This exciting position in AMD's Silicon IP solutions &amp; SOC group will provide the individual with an opportunity to demonstrate strong technical leadership across the design hierarchy from architecture to Productization. Join us in providing innovative IP solutions as we embark on our journey into the cutting edge programmable logic based silicon designs by&nbsp;delivering the complex IP Solutions for multiple market segments</span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">&nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">As an MTS you will work as part of a team responsible for all phases of product development including product definition and delivery. Member Technical Staff is expected to participate in and lead many aspects of a technical project including: thorough understanding of IP Architectural definition, u-Architecture development for individual IPs or IP subsystems, leading cross-functional IP teams from front-end development through Productization &amp; ASICization.</span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">&nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">This position requires an individual to be creative, team-oriented, technology savvy, able to lead large cross-functional teams, comfortable and willing to provide regular updates to management chain during the project execution&nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> &nbsp;</span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">THE PERSON:</span></strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> &nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">You have a passion for modern, complex hardware and IP architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.&nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> &nbsp;</span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">KEY RESPONSIBILITIES:</span></strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> &nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">&nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">A major part of your responsibility will be to participate in and take a lead technical role in most of the phases of the product development cycle from new product exploration, architecture through implementation, prototyping, validation and support including:&nbsp;</span></p><ul style="margin-top: 0in;"><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Define u-architecture from the architecture definition</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Evaluating and executing design and development plans for IPs&nbsp;</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">RTL design, IP Integration &amp; documentation&nbsp;</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Participating in and acting as a senior technical reviewer for various u-architecture and implementation reviews within the development organization</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Working with stakeholders to develop comprehensive testing plans including Compliance and Interop testing</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Critically Review and provide feedback on the Design Implementations and Verification plans</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Acting as technical mentor to junior engineers</span></li></ul><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> &nbsp;</span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">PREFERRED EXPERIENCE:</span></strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> &nbsp;</span></p><ul style="margin-top: 0in;"><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">A minimum of 8 years of experience is required.&nbsp;</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Proven experience in Silicon IP development process, methodologies, Design&nbsp;for&nbsp;Test methodologies</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Experience with Verilog RTL design, VCS simulation tool, Perl/Shell scripting</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Proven experience in contributing to complex silicon tapeouts</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Detailed understanding and proven track record of developing any of the leading edge PCIe, Full featured DMAs, NVMe based Storage IP, networking IP solutions such as Ethernet, TCP/IP, RDMA IPs.</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Strong oral and written communication skills are essential</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">The ideal candidate will be a proactive contributor to the RTL design methodologies&nbsp;</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">Ability to work on complex issues where analysis situations or data requires an in-depth evaluation of variable factors.</span></li><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">To be successful, this individual must demonstrate favorable results through leadership and influencing multiple individuals and groups.&nbsp;</span></li></ul><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> &nbsp;</span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">ACADEMIC CREDENTIALS:</span></strong><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"> &nbsp;</span></p><ul style="margin-top: 0in;"><li><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;">A Bachelor of Science Degree in Electrical Engineering or Computer Science, a master&rsquo;s degree or equivalent experience is required.</span></li></ul><p><span style="font-size: 11.0pt; font-family: 'Arial',sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="line-height: 107%;">#LI-PP2</span></span></span></p>

Collected experience requirement

8+ years