Staff/Principal Engineer - AI/ML & System-Level Validation

<strong class="jdheading"></strong><br><br><p style="margin: 0px; padding: 0px; color: windowtext;"><strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">WHAT YOU DO AT AMD CHANGES EVERYTHING</span></span></strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-ccp-props="{}"> </span></p><p style="margin: 0px; padding: 0px; color: windowtext;"><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, </span><span style="margin: 0px; padding: 0px;">gaming</span><span style="margin: 0px; padding: 0px;"> and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human </span><span style="margin: 0px; padding: 0px; border-bottom: 1px solid transparent;">ingenuity</span><span style="margin: 0px; padding: 0px;"> and a shared passion to create something extraordinary. When you join AMD, </span><span style="margin: 0px; padding: 0px;">you’ll</span><span style="margin: 0px; padding: 0px;"> discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.</span><span style="margin: 0px; padding: 0px;"> </span></span><strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">Together, we advance your career. </span></span></strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-ccp-props="{}"> </span></p> <br><strong class="jdheading"></strong><br><br><p style="margin: 0px;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Principal Member of Technical Staff — ROCm Validation & System-Level Quality</strong></span></p><p style="margin: 0px;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong> </strong></span></p><p style="margin: 0px;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>About the Role</strong></span></p><p style="margin: 0px;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">We are seeking a <strong>Principal Member of Technical Staff (PMTS)</strong> to serve as the senior technical leader for <strong>ROCm software validation</strong> across compute workloads and server-class systems. In this individual-contributor leadership role, you will define <em>how AMD proves ROCm is ready to ship</em> — from unit and component testing, through full-stack workload validation, to multi-node system-level qualification on AMD Instinct™ GPU platforms. You will set the technical direction for validation strategy, build and evolve the test infrastructure that gates every ROCm release, and personally drive the hardest debugging, characterization, and qualification problems. Your work directly determines the quality bar experienced by hyperscalers, OEMs, sovereign-AI customers, and the open-source community running ROCm in production.</span></p><p style="margin: 0px;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>What You Will Do</strong></span></p><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Own the end-to-end validation architecture</strong> for ROCm — unit, integration, framework, workload, performance, stress, stability, scale-out, and system-level test layers — across multiple GPU generations and server platforms.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Define release-qualification gates and exit criteria</strong> for ROCm software releases (functional coverage, performance regressions, stability hours, scale targets, RAS criteria) and drive the org to meet them.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Lead system-level testing for server nodes</strong> — multi-GPU topologies, PCIe/Infinity Fabric/xGMI, BMC/IPMI, thermal/power, firmware interactions, and multi-node fabric (Ethernet/InfiniBand/UALink) bring-up and validation.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Drive compute workload validation and characterization</strong> — LLM training and inference (PyTorch, vLLM, Triton, JAX), recommender systems, scientific HPC kernels, MLPerf-class benchmarks — establishing reproducible methodology, baselines, and regression tracking.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Architect the test infrastructure</strong> — distributed test runners, GitHub Actions / Jenkins / internal CI fleets, hardware lab orchestration, result data lakes, flaky-test detection, bisection automation, and self-service developer pre-submit pipelines.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Champion modern, agile quality engineering</strong> — shift-left testing, test pyramids, contract testing between layers, hermetic test environments, deterministic reproducers, and continuous validation in trunk.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Set the bar for GitHub-based quality workflows</strong> — PR gating policy, required checks, code-coverage standards, bug-bash and triage cadences, and disciplined issue management across ROCm/* repositories and partner upstream projects.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Lead complex escalation debug</strong> — partner with development, hardware, firmware, and customer-facing teams to root-cause the hardest multi-day, multi-node, multi-component failures and convert findings into durable test coverage.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Influence the roadmap</strong> — work with product management, silicon, platform, and software architecture to ensure validation readiness for next-generation Instinct GPUs and server platforms <em>before</em> tape-in milestones and silicon arrival.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Mentor and elevate</strong> Senior and Staff validation engineers, SDETs, and SQA leads; raise the technical bar through design review, code review, and written guidance.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Represent ROCm validation externally</strong> — strategic customer engagements, OEM qualification programs, and open-source community quality initiatives.</span></li></ul><p style="margin: 0px;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Minimum Qualifications</strong></span></p><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>12+ years</strong> of professional software engineering experience with a strong validation, SDET, or quality-engineering focus, including <strong>5+ years in a senior IC role</strong> (Staff/Principal/PMTS or equivalent) leading validation of complex systems software.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">BS/MS/PhD in Computer Science, Computer Engineering, or related discipline (or equivalent demonstrated experience).</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Expert-level <strong>Python</strong> for test automation and infrastructure; strong <strong>C++</strong> for debugging, and extending production code paths under test.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Deep, demonstrable validation experience in <strong>at least two</strong> of the following domains:</span></li></ul><ul><li style="margin-left: 0.75in; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">GPU compute software stacks (ROCm, CUDA, oneAPI, SYCL)</span></li><li style="margin-left: 0.75in; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Deep-learning frameworks and inference engines (PyTorch, TensorFlow, JAX, Triton, vLLM)</span></li><li style="margin-left: 0.75in; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">HPC / parallel runtimes and communication libraries (MPI, RCCL/NCCL, UCX, Libfabric)</span></li><li style="margin-left: 0.75in; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Linux kernel, GPU drivers, or accelerator firmware</span></li><li style="margin-left: 0.75in; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Distributed systems and large-scale cluster software</span></li><li style="margin-left: 0.75in; font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>System-level validation for server-class compute nodes</strong>— multi-GPU, multi-node, fabric-attached environments — including stress/stability, soak, fault-injection, and RAS testing.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Proven, hands-on experience working efficiently in an agentic AI engineering environment</strong> — daily, production use of LLM-based coding agents (e.g., Cursor, Claude Code, Copilot Workspace, Codex-class agents) and orchestration frameworks for real engineering work, with demonstrable productivity, quality, or coverage gains attributable to those workflows. Comfort designing prompts, tool/MCP integrations, evaluation harnesses, and guardrails for autonomous and semi-autonomous agents.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Hands-on experience defining and shipping <strong>release qualification programs</strong> for software consumed by hyperscalers, OEMs, or other Tier-1 customers.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Mastery of <strong>GitHub at scale</strong> for quality engineering — PR gating, GitHub Actions, self-hosted runners, required status checks, release tagging, and open-source contribution and triage norms.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong command of <strong>modern, agile software development practices</strong> — trunk-based development, CI/CD, shift-left testing, observability, feature flags, and incremental delivery — applied specifically to validation organizations.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Excellent written and verbal communication — able to author crisp test plans, qualification reports, RFCs, and post-mortems, and to influence development teams without authority.</span></li></ul><p style="margin: 0px;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Preferred Qualifications</strong></span></p><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Direct contributions to validation, CI, or test infrastructure for <strong>ROCm</strong>, <strong>PyTorch</strong>, <strong>LLVM</strong>, <strong>Triton</strong>, <strong>vLLM</strong>, or comparable upstream open-source projects.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Demonstrated leadership in agentic-AI adoption</strong> — built or rolled out agent-based workflows across an engineering team (e.g., autonomous test generation, AI-driven log/triage pipelines, multi-agent debug systems, MCP server design, retrieval-augmented engineering knowledge bases) with measurable outcomes.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience operating or validating <strong>large GPU clusters (256+ GPUs)</strong> — fabric bring-up, cluster health monitoring, and fleet-level diagnostics.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Familiarity with Training/Inference/HPC industry-standard benchmark methodologies and submissions.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Background in performance validation: roofline analysis, profiler tooling (rocprof, Omniperf, Nsight-class), regression detection</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with <strong>fault injection, RAS, telemetry</strong>, and long-haul stability programs for accelerator platforms.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Familiarity with hardware lab automation: BMC/IPMI/Redfish, PDU control, serial-console capture, automated re-imaging, and topology-aware test scheduling.</span></li></ul><ul style="margin-top: 0in;"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Prior experience standing up validation for <strong>pre-silicon / emulation / first-silicon bring-up</strong> of accelerators.</span></li></ul><p style="margin: 0px;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Why This Role</strong></span></p><p style="margin: 0px;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">ROCm powers AI and HPC workloads on AMD Instinct GPUs at the largest scale in the industry. The quality of every ROCm release is felt across millions of GPUs in production — and the validation organization is what stands between "code complete" and "customer ready." As Principal MTS for ROCm Validation, you will define that bar, build the systems that enforce it, and personally lead the toughest qualification problems on AMD's most strategic platforms.</span></p><p style="margin: 0px;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><em>AMD is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.</em></span></p><p style="margin: 0px;"> </p><p style="margin: 0px;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">#LI-NR1</span></p> <br><strong class="jdheading"></strong><br><br><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">Benefits offered are described: </span></em><span style="font-family: 'Arial',sans-serif; color: black;"><a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>.</span></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.</span></em></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a></span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;"> </span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">This posting is for an existing vacancy.</span></em></span></p>