Post‑Silicon SoC & System‑Level Validation Engineer
AMD · Bangalore
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Employer requisition: 81139
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Collected role description
<strong class="jdheading"></strong><br><br><p style="margin: 0px; padding: 0px; color: windowtext;"><strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">WHAT YOU DO AT AMD CHANGES EVERYTHING</span></span></strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-ccp-props="{}"> </span></p><p style="margin: 0px; padding: 0px; color: windowtext;"><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, </span><span style="margin: 0px; padding: 0px;">gaming</span><span style="margin: 0px; padding: 0px;"> and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human </span><span style="margin: 0px; padding: 0px; border-bottom: 1px solid transparent;">ingenuity</span><span style="margin: 0px; padding: 0px;"> and a shared passion to create something extraordinary. When you join AMD, </span><span style="margin: 0px; padding: 0px;">you’ll</span><span style="margin: 0px; padding: 0px;"> discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.</span><span style="margin: 0px; padding: 0px;"> </span></span><strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">Together, we advance your career. </span></span></strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-ccp-props="{}"> </span></p> <br><strong class="jdheading"></strong><br><br><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Role Overview :</strong></span></p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">This role focuses on validating <strong>end‑to‑end system behavior</strong>, ensuring that <strong>multiple SoC subsystems interact correctly under real customer and system‑level use cases</strong>.</span></p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"> </p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"> </p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>KEY RESPONSIBILITIES:</strong> </span></p><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Own <strong>SoC‑level post‑silicon validation</strong>, focusing on <strong>interaction between multiple subsystems</strong> rather than isolated IP testing.</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Validate <strong>end‑to‑end system flows</strong> involving CPU cores, on‑chip memories, NoC/interconnect, IOs, power management, and firmware.</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Ensure correct behavior across <strong>boot, runtime, stress, error, and recovery scenarios</strong> at the SoC level.</span></li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Develop <strong>validation test cases based on customer use cases </strong> (boot flows, IO usage, stress, concurrency, power transitions) into executable validation plans.</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Debug & root cause analysis:</strong> Perform <strong>deep SoC‑level debug</strong> to isolate failures across hardware, firmware, and system software boundaries</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Lab execution & characterization:</strong> Use engineering lab equipment (oscilloscopes, protocol analyzers, signal generators, etc.) to validate and debug functional behavior</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Documentation & reporting:</strong> Produce clear test plans, execution reports, failure analysis summaries, and status updates; track bugs/issues to closure</span></li></ul><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"> </p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>QUALIFICATIONS:</strong></span></p><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Experience</strong> in <strong>pre‑silicon and/or post‑silicon SoC validation</strong>, with strong ownership in post‑silicon execution.</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Strong understanding of <strong>SoC architecture and subsystem interactions</strong>.</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Experience validating <strong>system‑level use cases and customer‑driven scenarios</strong>.</span></li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Familiarity with <strong>debug tools</strong>, system logs, traces, and lab‑based validation setups</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Strong understanding of <strong>SoC boot flows, firmware, and HW/SW interaction</strong>.</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Lab proficiency:</strong> Extensive experience using lab equipment such as oscilloscopes, protocol analyzers, signal generators, etc.</span></li></ul><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"> </p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Preferred Qualifications :</span></p><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Experience with <strong>emulation platforms</strong> (Palladium, Protium, Zebu) for pre‑silicon or early validation.</span></li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Exposure to <strong>NoC fabrics, power management, clock/reset architecture, and system controllers</strong>. </span></li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Familiarity with system software stacks (bootloader, Linux, RTOS) and their interaction with silicon.</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Hands on experience using AI tools</span></li></ul><p style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-family: Aptos, sans-serif;"> </p><p style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-family: Aptos, sans-serif;"> </p><p style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-family: Aptos, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">#LI-NS2</span></p> <br><strong class="jdheading"></strong><br><br><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">Benefits offered are described: </span></em><span style="font-family: 'Arial',sans-serif; color: black;"><a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>.</span></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.</span></em></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a></span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;"> </span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">This posting is for an existing vacancy.</span></em></span></p>
Collected minimum qualification
<p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">Benefits offered are described: </span></em><span style="font-family: 'Arial',sans-serif; color: black;"><a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>.</span></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.</span></em></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a></span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;"> </span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">This posting is for an existing vacancy.</span></em></span></p>
Collected preferred qualification
<p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Role Overview :</strong></span></p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">This role focuses on validating <strong>end‑to‑end system behavior</strong>, ensuring that <strong>multiple SoC subsystems interact correctly under real customer and system‑level use cases</strong>.</span></p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"> </p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"> </p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>KEY RESPONSIBILITIES:</strong> </span></p><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Own <strong>SoC‑level post‑silicon validation</strong>, focusing on <strong>interaction between multiple subsystems</strong> rather than isolated IP testing.</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Validate <strong>end‑to‑end system flows</strong> involving CPU cores, on‑chip memories, NoC/interconnect, IOs, power management, and firmware.</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Ensure correct behavior across <strong>boot, runtime, stress, error, and recovery scenarios</strong> at the SoC level.</span></li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Develop <strong>validation test cases based on customer use cases </strong> (boot flows, IO usage, stress, concurrency, power transitions) into executable validation plans.</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Debug & root cause analysis:</strong> Perform <strong>deep SoC‑level debug</strong> to isolate failures across hardware, firmware, and system software boundaries</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Lab execution & characterization:</strong> Use engineering lab equipment (oscilloscopes, protocol analyzers, signal generators, etc.) to validate and debug functional behavior</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Documentation & reporting:</strong> Produce clear test plans, execution reports, failure analysis summaries, and status updates; track bugs/issues to closure</span></li></ul><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"> </p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>QUALIFICATIONS:</strong></span></p><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Experience</strong> in <strong>pre‑silicon and/or post‑silicon SoC validation</strong>, with strong ownership in post‑silicon execution.</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Strong understanding of <strong>SoC architecture and subsystem interactions</strong>.</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Experience validating <strong>system‑level use cases and customer‑driven scenarios</strong>.</span></li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Familiarity with <strong>debug tools</strong>, system logs, traces, and lab‑based validation setups</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Strong understanding of <strong>SoC boot flows, firmware, and HW/SW interaction</strong>.</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 12pt;"><strong>Lab proficiency:</strong> Extensive experience using lab equipment such as oscilloscopes, protocol analyzers, signal generators, etc.</span></li></ul><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"> </p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Preferred Qualifications :</span></p><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Experience with <strong>emulation platforms</strong> (Palladium, Protium, Zebu) for pre‑silicon or early validation.</span></li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Exposure to <strong>NoC fabrics, power management, clock/reset architecture, and system controllers</strong>. </span></li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Familiarity with system software stacks (bootloader, Linux, RTOS) and their interaction with silicon.</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Hands on experience using AI tools</span></li></ul><p style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-family: Aptos, sans-serif;"> </p><p style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-family: Aptos, sans-serif;"> </p><p style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-family: Aptos, sans-serif;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">#LI-NS2</span></p>