Post Silicon Validation Manager

AMD · Bangalore

Source and collection record

Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 75217

Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.

How sourcing and classification work · Report a discrepancy

Your application evidence checklist

Mark the statements you can support after reading the employer source. This checklist stays on this page; it does not score your eligibility or submit an application.

Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

0 of 3 checks marked. Keep unresolved requirements as questions for the employer.

Collected role description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Roles & Responsibilities: <ul style="margin-bottom: 0in; margin-top: 0px;"><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Take responsibility for the Post silicon validation scope and plan for IPs like HSIO, Memory, RAS, Cores, LSIO, Power Management, Multimedia etc. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Ensure robust planning at the pre-silicon stage, working with DV or Emulation teams and support the Leads and engineers in framing the relevant test cases </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Support the team with the right infrastructure at the right time </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Define the scaling of the teams for Capability and Capacity in line with the BU’s growth </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Bigger picture planning for roadmaps and process improvements </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Create a cohesive culture of openness, diversity, technical growth for the team members </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Act with great resolve during testing times of critical issues, milestones, customer escalations and BU related internal changes </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Exhibit strong leadership qualities to take the team forward towards growth and achieving the mission of the company </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Exhibit great technical depth in the post silicon validation to take the right technical decisions for the team </li></ul> Individual requirements: <ul style="margin-bottom: 0in; margin-top: 0px;"><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Highly skilled engineering professional with over 15 years of experience.</li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Solid experience in handling high performing, dynamic and a strong technical team. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Solid Experience and Knowledge in the post silicon validation of x86 IPs like Cores, Memory, RAS, HSIO. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Solid experience in handling the growth charter for growing teams and embrace changes with ease and grace </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Adept in calling out risks while anticipating issues and coming up with appropriate mitigation plans </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Experienced in working with the Enablement Manager and Leads, Program Managers, Product Managers, BIOS/FW Managers and other cross functional stakeholders and create a robust alignment setup while running execution. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Preferred experience working with cross-functional teams like DV/Silicon Designers/Pre-silicon/Platform/BIOS/FW/ SW. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Experience in High Speed I/Os like PCIe (preferably Gen4 and above), Memory (DDR4/DDR5.LPDDR4/LPDDR5), USB4.0/3.2/3.1, USB PD, USB Type C, Display interfaces and Ethernet and high-speed interconnects. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Experience in Power Management, Power Delivery, and Power Measurements. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Hands-on high speed and board measurement techniques in using high end equipment like Oscilloscopes, Logic Analyzers, Debugger tools, Raspberry PI, Network analyzers, etc. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Preferred experience with scripting using TCL, Python </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Excellent communication, collaboration, articulation, upleveling to senior management and team playing skills. </li></ul> Key responsibilities: <ul style="margin-bottom: 0in; margin-top: 0px;"><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Ensuring the team delivers error free and timely delivery of test cases and test reports, meeting or beating the program commitment </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Synergize with the Pre-silicon and DV teams and other stakeholders for proper interception of milestones and risk callouts. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Actively participate in discussions with cross-functional teams in defining and refining test plans and guiding the team for the right path. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Be on top of all issues pertinent to Debug & Triage of any functional issues specific across the entire validation cycle </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Drive meetings for issue closures and actively track schedules and milestone quality metrics </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Ensure the Best in class Documentation and collateral delivery from the team. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Engage with the QA Validation and CAE teams for seamless handing over of test plans or reports, as relevant. </li></ul> #LI-NS2 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

Roles & Responsibilities:   <ul style="margin-bottom: 0in; margin-top: 0px;"><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Take responsibility for the Post silicon validation scope and plan for IPs like HSIO, Memory, RAS, Cores, LSIO, Power Management, Multimedia etc. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Ensure robust planning at the pre-silicon stage, working with DV or Emulation teams and support the Leads and engineers in framing the relevant test cases </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Support the team with the right infrastructure at the right time </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Define the scaling of the teams for Capability and Capacity in line with the BU’s growth </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Bigger picture planning for roadmaps and process improvements </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Create a cohesive culture of openness, diversity, technical growth for the team members  </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Act with great resolve during testing times of critical issues, milestones, customer escalations and BU related internal changes </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Exhibit strong leadership qualities to take the team forward towards growth and achieving the mission of the company </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Exhibit great technical depth in the post silicon validation to take the right technical decisions for the team </li></ul>   Individual requirements:  <ul style="margin-bottom: 0in; margin-top: 0px;"><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Highly skilled engineering professional with over 15 years of experience.</li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Solid experience in handling high performing, dynamic and a strong technical team. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Solid Experience and Knowledge in the post silicon validation of x86 IPs like Cores, Memory, RAS, HSIO. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Solid experience in handling the growth charter for growing teams and embrace changes with ease and grace </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Adept in calling out risks while anticipating issues and coming up with appropriate mitigation plans </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Experienced in working with the Enablement Manager and Leads, Program Managers, Product Managers, BIOS/FW Managers and other cross functional stakeholders and create a robust alignment setup while running execution. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Preferred experience working with cross-functional teams like DV/Silicon Designers/Pre-silicon/Platform/BIOS/FW/ SW. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Experience in High Speed I/Os like PCIe (preferably Gen4 and above), Memory (DDR4/DDR5.LPDDR4/LPDDR5), USB4.0/3.2/3.1, USB PD, USB Type C, Display interfaces and Ethernet and high-speed interconnects. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Experience in Power Management, Power Delivery, and Power Measurements. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Hands-on high speed and board measurement techniques in using high end equipment like Oscilloscopes, Logic Analyzers, Debugger tools, Raspberry PI, Network analyzers, etc. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Preferred experience with scripting using TCL, Python </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Excellent communication, collaboration, articulation, upleveling to senior management and team playing skills. </li></ul> Key responsibilities:  <ul style="margin-bottom: 0in; margin-top: 0px;"><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Ensuring the team delivers error free and timely delivery of test cases and test reports, meeting or beating the program commitment </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Synergize with the Pre-silicon and DV teams and other stakeholders for proper interception of milestones and risk callouts. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Actively participate in discussions with cross-functional teams in defining and refining test plans and guiding the team for the right path. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Be on top of all issues pertinent to Debug & Triage of any functional issues specific across the entire validation cycle  </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Drive meetings for issue closures and actively track schedules and milestone quality metrics </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Ensure the Best in class Documentation and collateral delivery from the team. </li><li style="margin: 0in 0in 0in 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Engage with the QA Validation and CAE teams for seamless handing over of test plans or reports, as relevant. </li></ul>   #LI-NS2

Collected experience requirement

15+ years