Sr. Staff Engineer – Power Lead, Systems Architecture | Qualcomm

Lead system power architecture for target So Cs and platforms from concept development through architecture freeze, design convergence, pre-silicon readiness, post-silicon characterization, and learning closure. Translate product requirements, use cases, workload behavior, concurrency, duty cycles, thermal constraints, and performance KPIs into system-level power requirements and architecture decisions. Define and analyze system power states, power islands, retention strategies, clock- and power-gating behavior, wake/sleep flows, operating points, DVFS policies, and cross-IP power-management interactions. Establish top-down system power budgets and projections and work with IP teams to decompose targets, assumptions, modes, activity profiles, and optimization requirements. Develop or guide workload-driven analytical, simulation, empirical, or hybrid models for power and performance projection. Evaluate architectural options across power, performance, thermal behavior, area, latency, responsiveness, complexity, risk, and user-experience objectives. Perform workload, use-case, concurrency, utilization, traffic, and data-movement analysis to identify system-level optimization opportunities. Drive cross-IP power optimization involving compute, memory, interconnect, multimedia, connectivity, peripherals, system infrastructure, firmware, and software policies. Track gaps between targets and projections; lead technical investigations, root-cause analysis, mitigation planning, risk assessment, and issue closure. Integrate IP-level models and implementation evidence into coherent system projections while making assumptions, model fidelity, uncertainty, and confidence ranges explicit. Define architecture validation and measurement requirements so that pre-silicon hypotheses can be verified on emulation, prototypes, boards, and production silicon. Correlate pre-silicon models and estimates with post-silicon rail, workload, telemetry, and performance measurements; explain material variances and feed calibrated models and architecture actions into subsequent products. Partner with So C architecture, performance/modeling, IP architecture, RTL design, DV, physical design, firmware, software, thermal, validation, lab, and silicon teams. Communicate system power status, trade-offs, risks, recommendations, and closure plans to technical and program stakeholders. Develop reusable power-architecture methods, workload definitions, model standards, projection practices, dashboards, and review criteria. Bachelor's degree in Engineering, Electrical/Electronics Engineering, Computer Engineering, Computer Science, Information Systems, or a related field and 10+ years of Systems Engineering, So C Architecture, Power Architecture, Performance/Power Analysis, or related experience; or Master's degree in a related field and 8+ years of relevant experience; or Ph D in a related field and 5+ years of relevant experience. Approximately 10+ years of relevant industry experience is preferred. Strong understanding of So C and computer architecture, including compute subsystems, memory hierarchy, interconnects, system infrastructure, I/O, clock/reset, and HW/SW interaction. Experience in system power architecture, workload-based power analysis, power-performance analysis, system modeling, projection, optimization, or post-silicon power characterization. Ability to reason about dynamic and leakage power, operating modes, utilization, duty cycle, voltage/frequency operating points, concurrency, and thermal or sustained-performance effects. Demonstrated ability to lead cross-functional technical investigations and convert analysis into architecture or optimization decisions. Strong analytical, problem-solving, technical-communication, and stakeholder-leadership skills. Experience defining So C or subsystem power states, islands, low-power modes, sleep/idle behavior, wake-up paths, retention, power gating, clock gating, or DVFS. Experience with representative CPU, GPU, DSP, NPU/AI, memory, interconnect, multimedia, connectivity, peripheral, or full-platform workloads. Hands-on experience with power/performance modeling, sensitivity analysis, projection, workload characterization, trace analysis, scripting, or large-data analysis. Experience correlating architecture models and pre-silicon estimates with post-silicon measurements and driving variance root cause and model calibration. Familiarity with rail-level power measurements, silicon telemetry, performance counters, profiling, lab measurement methods, board bring-up, or system debugging. Working knowledge of RTL/gate-level power inputs, activity factors, leakage/dynamic splits, corners, implementation data, or power-estimation tools. Awareness of UPF/CPF, power-domain crossings, isolation, level shifting, retention, structural low-power verification, synthesis, timing, or physical-design power considerations. Understanding of PMICs, regulators, power rails, PDN/power-grid considerations, thermal management, and their relationship to So C operating policy. Familiarity with Linux/Android, firmware, device drivers, system traces, power-management software, or Python/shell-based automation. Prior So C architecture, subsystem architecture, IP microarchitecture, design, validation, or silicon-debug experience. Demonstrated technical leadership across distributed teams, including the ability to align stakeholders and influence decisions without direct authority. Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience. OR Ph D in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. 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