Principal Engineer Design

Infineon · Bangalore

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Last observed by our collector: 9 October 2026 at 12:49 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: HRC1715359

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Collected role description

#WeAreIn to transform theoretical concepts into real hardware designs. Are you in? Your role Key responsibilities in your new roleAs an engineer, Timing Closure, and Constraints Coding/Validation Engineer, you will own the architectural timing intent, constraint hygiene, and complete timing sign-off for complex, multi-million gate SoCs. You will drive multi-mode multi-corner (MMMC) timing closure from block-level implementation up to full-chip integration. A core focus of this role is using advanced optimization tools to fix critical setup, hold, transition and crosstalk violations across both functional and complex DFT modes (Scan, At-Speed, MBIST etc). <ul style="box-sizing: border-box; margin-top: 0px; margin-bottom: 10px; font-family: Arial;"><li style="box-sizing: border-box;">Timing Closure & ECO Sign-off: Lead and execute block-level and full-chip flat/hierarchical timing closure across advanced process nodes. Generate engineering change orders (ECOs) to fix setup, hold, max transition, and signal integrity violations</li><li style="box-sizing: border-box;">Tool-Driven Optimization: Demonstrate expert mastery over automated ECO fixing tools (Tweaker, PT DMSA/Primeclosure, Cadence Tempus) drive rapid convergence of complex bottleneck violation</li><li style="box-sizing: border-box;">Multi-Signoff STA Infrastructure: Architect, set up, and execute robust MMMC sign-off environments using Synopsys PrimeTime (PT/PT-PX) and Cadence Tempus. Ensure complete correlation across different timing engines</li><li style="box-sizing: border-box;">Hierarchical Constraint Management: Architect, generate, and maintain clean SDC files at both the Block/IP level and the Full-Chip Top level. Manage constraint promotion, demotion, and validation</li><li style="box-sizing: border-box;">Signal Integrity & Noise Analysis: Strong understanding of crosstalk-induced noise, glitch propagation, signal electromigration (Signal EM), and managing reconvergent timing paths affected by crosstalk delay</li><li style="box-sizing: border-box;">DFT Mode Timing Validation: Define, audit, and validate constraints across multiple operational modes, specifically targeting Scan Shift & Capture, At-Speed Testing, Memory BIST (MBIST), and Logic BIST (LBIST) concurrent execution modes</li><li style="box-sizing: border-box;">Cross-Functional Leadership: Collaborate with DFT Engineers to resolve test mode constraints, RTL Designers to fix structural CDC/RDC violations, and P&R Teams to guide placement, clock-tree synthesis (CTS), and routing optimization</li><li style="box-sizing: border-box;">Automation & Flow Development: Write advanced, production-grade Tcl scripts for PrimeTime/Tempus environments</li><li style="box-sizing: border-box;">Utilize Python or Perl to build regression suites, analyze timing violations, and compare SDC variations </li></ul> Your profile Qualifications and skills to help you succeed <ul style="box-sizing: border-box; margin-top: 0px; margin-bottom: 10px; font-family: Arial;"><li style="box-sizing: border-box;">Bachelor’s or Master’s degree in Electrical/Electronics Engineering, VLSI, Microelectronics, or a related field.</li><li style="box-sizing: border-box;">Minimum 13+ years of relavent experience in STA full chip </li><li style="box-sizing: border-box;">Core Tool Expertise (Mandatory):<ul style="margin-top: 0cm; box-sizing: border-box; margin-bottom: 0px; font-family: Arial;" type="circle"><li style="box-sizing: border-box;">Sign-off STA: Synopsys PrimeTime (PT/PT-PX) and Cadence Tempus.</li><li style="box-sizing: border-box;"> Timing Closure / ECO: Cadence Tempus, Synopsys PrimeTime/PrimeClosure & Tweaker</li><li style="box-sizing: border-box;"> Constraints Validation: Synopsys TCM/GCA, Ausdia TimeVision, SpyGlass Constraints, or Cadence CCD</li></ul></li><li style="box-sizing: border-box;">Run strict constraints verification using industry-standard tools (Synopsys TCM, SpyGlass Constraints, or Cadence CCD) to eliminate unconstrained paths, incorrect clock-gating checks, and conflicting case analysis settings between functional and DFT model</li><li style="box-sizing: border-box;">Hands-on experience reading, writing, and parsing Unified Power Format (UPF) constraints to validate low-power design architectures (e.g., power-gating, isolation cells, retention registers, and level-shifter placement</li><li style="box-sizing: border-box;">Familiarity with Logic Equivalency Checking using industry tools like Cadence Conformal LEC or Synopsys Formality to verify that optimization/ECO steps maintain functional equivalence </li><li style="box-sizing: border-box;">Deep understanding of advanced node variation models (POCV/LVF), temperature inversion, crosstalk/noise analysis, and hierarchical top-level clock distribution networks</li><li style="box-sizing: border-box;">Solid comprehension of DFT architecture, test clock structures, multiplexer-heavy clock networks, and asynchronously driven test logic</li><li style="box-sizing: border-box;">Expert proficiency in Tcl (highly critical for runtime timing script customization) and Python/Perl for automated data mining and constraint auditing</li></ul> #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. Our hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.Please let your recruiter know if you need any accommodations during the interview process.Learn more about our various <a href="https://www.infineon.com/cms/en/about-infineon/company/contacts/" target="_blank" style="box-sizing: border-box; background-color: transparent; color: inherit; text-decoration: underline; cursor: pointer; user-select: auto; font-size: 14px;">contact channels</a> and about <a href="https://www.infineon.com/cms/en/careers/diversity-and-inclusion/" target="_blank" style="box-sizing: border-box; background-color: transparent; color: inherit; text-decoration: underline; cursor: pointer; user-select: auto; font-size: 14px;">Diversity & Inclusion</a> at Infineon. Gowri Shenoy https://www.linkedin.com/in/gowri-shenoy-33894217/

Collected experience requirement

13+ years