Principal Silicon Engineer

Microsoft · Remote

Source and collection record

Last observed by our collector: 9 October 2026 at 12:51 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 200044509

Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.

How sourcing and classification work · Report a discrepancy

Your application evidence checklist

Mark the statements you can support after reading the employer source. This checklist stays on this page; it does not score your eligibility or submit an application.

Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

0 of 2 checks marked. Keep unresolved requirements as questions for the employer.

Collected role description

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission.The Data Processing Unit (DPU) team brings together state-of-the-art software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to its integrated design, this solution empowers teams to operate with increased agility and deliver significantly superior performance compared to CPU-based alternatives We’re seeking a Full-chip Integration experience professionals with solid understanding of C4/package interfaces, chip finishing, and RDL & power delivery. As part of our DPU silicon team, you’ll take on the challenge of driving our fullchip integration execution from early design exploration to signoff. You’ll work across teams to define, develop, and drive all aspects of power & signal planning, RDL optimization, and packaging interface. We’re working on some of the most exciting silicon projects in Microsoft, and you will help us drive our vision. Responsibilities <ul><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Take ownership and responsibility for our fullchip/package integration</li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Take an active role in early-phase design planning with die size planning, floorplanning, C4/microbump development, and RDL insertion & optimization</li><li>Develop, enhance, and maintain full-chip integration methodologies; collaborate with vendors and partners to align workflows with industry practices, address tool-related issues, and improve the reliability and efficiency of full-chip finishing and integration processes.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Define & drive to integration milestones across project phases; manage interaction and integration with package team & vendors to ensure continuity of entire system design</li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Manage multiple power domains & islands, ensuring correctness and robustness of the design</li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Ensure a convergent integration process and drive package closure through all phases including final signoff for tapeout</li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Work across teams to identify and resolve power delivery issues, integration issues, etc; provide guidance for floorplan adjustments to address power integrity issues and continuity of the package and board design</li></ul> Qualifications Required qualifications:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Bachelor’s degree in computer engineering, electrical engineering, or related field</li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">7+ years of physical design experience with focus on C4 integration & chip finishing</li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Experience with ASIC design tools (e.g., DC, ICC2/Fusion-Compiler, PrimeTime) & Physical Verification tools (e.g., Calibre)</li></ul>Preferred qualifications:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">10+ years of hands-on physical design experience with focus on C4/RDL integration, chip finishing, and signoff</li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Deep expertise in power planning, C4/microbump deployment and chip/package interfaces</li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Proficiency in flow automation, scripting (TCL/Perl) & tool debug</li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Ability to develop & maintain package signoff checklists, to track and report fullchip integration progress through all design phases, and successfully execute chip closure on schedule</li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Demonstrated tapeout experience in TSMC 5nm process or below</li></ul> This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. <hr> Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about <a href="https://careers.microsoft.com/v2/global/en/accessibility.html">requesting accommodations.</a>

Collected experience requirement

7+ years