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DFT

TCS · Bangalore

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Last observed by our collector: . This is not a manual review or a confirmation from the employer.

Employer requisition: 431648

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Collected role description

About the Unit TCS IAE is redefining the future of industry by embedding intelligence across engineering, manufacturing, asset, and service value chains. Powered by AI, connected ecosystems, and autonomous operations, it transforms insights into action—creating self-optimizing, resilient, and intelligent enterprises at scale. By seamlessly converging the physical and digital worlds, TCS IAE is enabling a new era of AI-first enterprises where systems continuously learn, adapt, and evolve—driving measurable outcomes and shaping how industries operate for the future. Role: Design For Test (DFT) Roles & Responsibilities · Plan and implement DFT architectures for ASIC/SoC designs · Insert and validate scan chains, scan compression, and test modes · Generate and analyze ATPG patterns for various fault models · Implement and debug MBIST/LBIST and memory repair flows · Perform DFT simulations and debug test coverage issues · Collaborate with PD, STA, and Validation teams for test-friendly closure · Support silicon bring-up, wafer sort, and production test readiness Tools & Skills · DFT Tools: Siemens Tessent, Cadence Modus, Synopsys DFTMAX · ATPG: Stuck-at, Transition, Path Delay, Bridging fault models · Standards: IEEE 1149.1 (JTAG), IEEE 1687 (IJTAG) · Simulation: VCS, Questa, NCsim · Verification: LEC (Conformal), Lint/CDC tools · Scripting: Tcl (mandatory), Perl / Python / Shell</p

Collected minimum qualification

BACHELOR OF TECHNOLOGY

Collected experience requirement

3 - 15 Years