FPGA

About the Unit TCS IAE is redefining the future of industry by embedding intelligence across engineering, manufacturing, asset, and service value chains. Powered by AI, connected ecosystems, and autonomous operations, it transforms insights into action—creating self-optimizing, resilient, and intelligent enterprises at scale. By seamlessly converging the physical and digital worlds, TCS IAE is enabling a new era of AI-first enterprises where systems continuously learn, adapt, and evolve—driving measurable outcomes and shaping how industries operate for the future. Role: FPGA Design Engineer Roles & Responsibilities · Design and implement FPGA RTL using Verilog, VHDL, or SystemVerilog · Perform FPGA synthesis, place & route, and timing closure · Handle multi-clock and clock domain crossing (CDC) scenarios · Integrate standard protocols such as AXI, APB, I2C, SPI, and UART · Develop testbenches and perform FPGA-level simulation and debug · Support FPGA bring-up, board-level debug, and performance validation · Collaborate with ASIC/SoC teams for RTL correlation and emulation use cases · Automate FPGA flows using Tcl, Python, or Shell scripts Tools & Skills · FPGA Tools: Xilinx Vivado, Vivado HLS, Intel Quartus · Languages: Verilog, VHDL, SystemVerilog · Protocols: AXI, APB, PCIe (as applicable), I2C, SPI, UART · Debug: Integrated Logic Analyzer (ILA), SignalTap · Platforms: Xilinx UltraScale / UltraScale+, RFSoC, Intel Agilex · Scripting: Tcl, Python, Shell</p